22 #ifndef VMCS_INTEL_X64_VMM_STATE_H 23 #define VMCS_INTEL_X64_VMM_STATE_H 77 {
return g_gdt.
base(); }
79 {
return g_idt.
base(); }
82 {
return g_gdt.
limit(); }
84 {
return g_idt.
limit(); }
87 {
return g_gdt.
limit(m_cs_index); }
89 {
return g_gdt.
limit(m_ss_index); }
91 {
return g_gdt.
limit(m_fs_index); }
93 {
return g_gdt.
limit(m_gs_index); }
95 {
return g_gdt.
limit(m_tr_index); }
109 {
return g_gdt.
base(m_cs_index); }
111 {
return g_gdt.
base(m_ss_index); }
113 {
return g_gdt.
base(m_fs_index); }
115 {
return g_gdt.
base(m_gs_index); }
117 {
return g_gdt.
base(m_tr_index); }
120 {
return m_ia32_pat_msr; }
122 {
return m_ia32_efer_msr; }
126 bfdebug <<
"----------------------------------------" << bfendl;
127 bfdebug <<
"- vmcs_intel_x64_vmm_state dump -" << bfendl;
128 bfdebug <<
"----------------------------------------" << bfendl;
131 bfdebug <<
"segment selectors:" << bfendl;
139 bfdebug <<
"segment base:" << bfendl;
147 bfdebug <<
"segment limit:" << bfendl;
155 bfdebug <<
"segment acess rights:" << bfendl;
163 bfdebug <<
"registers:" << bfendl;
169 bfdebug <<
"flags:" << bfendl;
173 bfdebug <<
"gdt/idt:" << bfendl;
180 bfdebug <<
"model specific registers:" << bfendl;
181 bfdebug <<
" - m_ia32_pat_msr: " <<
view_as_pointer(m_ia32_pat_msr) << bfendl;
182 bfdebug <<
" - m_ia32_efer_msr: " <<
view_as_pointer(m_ia32_efer_msr) << bfendl;
gdt_x64::base_type fs_base() const override
gdt_x64::access_rights_type cs_access_rights() const override
intel_x64::cr3::value_type cr3() const override
x64::segment_register::type tr() const override
intel_x64::cr4::value_type cr4() const override
access_rights_type access_rights(index_type index) const
gdt_x64::access_rights_type gs_access_rights() const override
idt_x64::size_type idt_limit() const override
gdt_x64::limit_type tr_limit() const override
gdt_x64::limit_type fs_limit() const override
gdt_x64::limit_type gs_limit() const override
x64::segment_register::type ss() const override
gdt_x64::base_type gs_base() const override
x64::segment_register::type fs() const override
intel_x64::msrs::value_type ia32_efer_msr() const override
vmcs_intel_x64_vmm_state()
gdt_x64::base_type tr_base() const override
gdt_x64::base_type cs_base() const override
uintptr_t integer_pointer
~vmcs_intel_x64_vmm_state() override=default
gdt_x64::base_type ss_base() const override
x64::segment_register::type cs() const override
uint32_t access_rights_type
intel_x64::cr0::value_type cr0() const override
x64::rflags::value_type rflags() const override
gdt_x64::limit_type cs_limit() const override
const void * view_as_pointer(const T val)
x64::segment_register::type gs() const override
gdt_x64::size_type gdt_limit() const override
integer_pointer base() const
intel_x64::msrs::value_type ia32_pat_msr() const override
void dump() const override
gdt_x64::integer_pointer gdt_base() const override
gdt_x64::access_rights_type ss_access_rights() const override
idt_x64::integer_pointer idt_base() const override
uintptr_t integer_pointer
gdt_x64::access_rights_type fs_access_rights() const override
gdt_x64::access_rights_type tr_access_rights() const override
gdt_x64::limit_type ss_limit() const override