gdt_x64.h

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//
// Bareflank Hypervisor
//
// Copyright (C) 2015 Assured Information Security, Inc.
// Author: Rian Quinn        <quinnr@ainfosec.com>
// Author: Brendan Kerrigan  <kerriganb@ainfosec.com>
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2.1 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA

#ifndef GDT_X64_H
#define GDT_X64_H

#include <gsl/gsl>

#include <vector>
#include <algorithm>
#include <exception>

#include <guard_exceptions.h>

// -----------------------------------------------------------------------------
// Global Descriptor Table Register
// -----------------------------------------------------------------------------

#pragma pack(push, 1)

struct gdt_reg_x64_t
{
    using limit_type = uint16_t;
    using base_type = uint64_t *;

    limit_type limit;
    base_type base;

    gdt_reg_x64_t() noexcept :
        limit(0),
        base(nullptr)
    {}

    gdt_reg_x64_t(base_type b, limit_type l) noexcept :
        limit(l),
        base(b)
    {}
};

#pragma pack(pop)

// -----------------------------------------------------------------------------
// Intrinsics
// -----------------------------------------------------------------------------

extern "C" void __read_gdt(gdt_reg_x64_t *gdt_reg) noexcept;
extern "C" void __write_gdt(gdt_reg_x64_t *gdt_reg) noexcept;

// -----------------------------------------------------------------------------
// GDT Functions
// -----------------------------------------------------------------------------

// *INDENT-OFF*

namespace x64
{
namespace gdt
{
    inline auto get() noexcept
    {
        auto &&reg = gdt_reg_x64_t{};
        __read_gdt(&reg);

        return reg;
    }

    inline void set(gdt_reg_x64_t::base_type base, gdt_reg_x64_t::limit_type limit) noexcept
    {
        auto &&reg = gdt_reg_x64_t{base, limit};
        __write_gdt(&reg);
    }

    namespace base
    {
        inline auto get() noexcept
        {
            auto &&reg = gdt_reg_x64_t{};
            __read_gdt(&reg);

            return reg.base;
        }

        inline void set(gdt_reg_x64_t::base_type base) noexcept
        {
            auto &&reg = gdt_reg_x64_t{};
            __read_gdt(&reg);

            reg.base = base;
            __write_gdt(&reg);
        }
    }

    namespace limit
    {
        inline auto get() noexcept
        {
            auto &&reg = gdt_reg_x64_t{};
            __read_gdt(&reg);

            return reg.limit;
        }

        inline void set(gdt_reg_x64_t::limit_type limit) noexcept
        {
            auto &&reg = gdt_reg_x64_t{};
            __read_gdt(&reg);

            reg.limit = limit;
            __write_gdt(&reg);
        }
    }
}
}

// *INDENT-ON*

// -----------------------------------------------------------------------------
// Global Descriptor Table
// -----------------------------------------------------------------------------

class gdt_x64
{
public:

    using size_type = uint16_t;
    using index_type = uint16_t;
    using integer_pointer = uintptr_t;
    using base_type = uint64_t;
    using limit_type = uint32_t;
    using access_rights_type = uint32_t;
    using segment_descriptor_type = uint64_t;

    gdt_x64() noexcept
    {
        guard_exceptions([&]
        {
            m_gdt_reg.base = x64::gdt::base::get();
            m_gdt_reg.limit = x64::gdt::limit::get();

            std::copy_n(m_gdt_reg.base, m_gdt_reg.limit >> 3, std::back_inserter(m_gdt));
        });
    }

    gdt_x64(size_type size) noexcept :
        m_gdt(size)
    {
        guard_exceptions([&]
        {
            m_gdt_reg.base = m_gdt.data();
            m_gdt_reg.limit = gsl::narrow_cast<size_type>(size << 3);
        });
    }

    ~gdt_x64() noexcept = default;

    integer_pointer base() const
    { return reinterpret_cast<integer_pointer>(m_gdt_reg.base); }

    size_type limit() const
    { return m_gdt_reg.limit; }

    void set_base(index_type index, base_type base)
    {
        segment_descriptor_type sd1 = 0;
        segment_descriptor_type sd2 = 0;

        expects(index != 0);

        sd1 = m_gdt.at(index);
        sd1 = (sd1 & 0x00FFFF000000FFFF);

        // The segment base description can be found in the Intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // Note that in 64bit mode, system descriptors are 16 bytes long
        // instead of the traditional 8 bytes. A system descriptor has the
        // system flag set to 0. Most of the time, this is going to be the
        // TSS descriptor. Even though Intel Tasks don't exist in 64 bit mode,
        // the TSS descriptor is still used, and thus, TR must still be loaded.
        //
        // ------------------------------------------------------------------
        // |                       Base 63-32                               |
        // ------------------------------------------------------------------
        // |   Base 31-24   |                              |   Base 23-16   |
        // ------------------------------------------------------------------
        // |          Base 15-00         |                                  |
        // ------------------------------------------------------------------
        //

        segment_descriptor_type base_15_00 = ((base & 0x000000000000FFFF) << 16);
        segment_descriptor_type base_23_16 = ((base & 0x0000000000FF0000) << 16);
        segment_descriptor_type base_31_24 = ((base & 0x00000000FF000000) << 32);
        segment_descriptor_type base_63_32 = ((base & 0xFFFFFFFF00000000) >> 32);

        if ((sd1 & 0x100000000000) == 0)
        {
            sd2 = m_gdt.at(index + 1U);
            sd2 = (sd2 & 0xFFFFFFFF00000000);

            m_gdt.at(index + 0U) = sd1 | base_31_24 | base_23_16 | base_15_00;
            m_gdt.at(index + 1U) = sd2 | base_63_32;
        }
        else
        {
            m_gdt.at(index + 0U) = sd1 | base_31_24 | base_23_16 | base_15_00;
        }
    }

    base_type base(index_type index) const
    {
        segment_descriptor_type sd1 = 0;
        segment_descriptor_type sd2 = 0;

        expects(index != 0);

        // The segment base description can be found in the Intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // Note that in 64bit mode, system descriptors are 16 bytes long
        // instead of the traditional 8 bytes. A system descriptor has the
        // system flag set to 0. Most of the time, this is going to be the
        // TSS descriptor. Even though Intel Tasks don't exist in 64 bit mode,
        // the TSS descriptor is still used, and thus, TR must still be loaded.
        //
        // ------------------------------------------------------------------
        // |                       Base 63-32                               |
        // ------------------------------------------------------------------
        // |   Base 31-24   |                              |   Base 23-16   |
        // ------------------------------------------------------------------
        // |          Base 15-00         |                                  |
        // ------------------------------------------------------------------
        //

        sd1 = m_gdt.at(index);
        base_type base_15_00 = ((sd1 & 0x00000000FFFF0000) >> 16);
        base_type base_23_16 = ((sd1 & 0x000000FF00000000) >> 16);
        base_type base_31_24 = ((sd1 & 0xFF00000000000000) >> 32);

        if ((sd1 & 0x100000000000) == 0)
        {
            sd2 = m_gdt.at(index + 1U);
            base_type base_63_32 = ((sd2 & 0x00000000FFFFFFFF) << 32);

            return base_63_32 | base_31_24 | base_23_16 | base_15_00;
        }

        return base_31_24 | base_23_16 | base_15_00;
    }

    void set_limit(index_type index, limit_type limit)
    {
        expects(index != 0);
        segment_descriptor_type sd1 = (m_gdt.at(index) & 0xFFF0FFFFFFFF0000);

        // The segment limit description can be found in the Intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // ------------------------------------------------------------------
        // |               | Limit 19-16 |                                  |
        // ------------------------------------------------------------------
        // |                             |            Limit 15-00           |
        // ------------------------------------------------------------------

        if ((sd1 & 0x80000000000000) != 0)
            limit = (limit >> 12);

        segment_descriptor_type limit_15_00 = ((static_cast<segment_descriptor_type>(limit) & 0x000000000000FFFF) << 0);
        segment_descriptor_type limit_19_16 = ((static_cast<segment_descriptor_type>(limit) & 0x00000000000F0000) << 32);

        m_gdt.at(index) = sd1 | limit_19_16 | limit_15_00;
    }

    limit_type limit(index_type index) const
    {
        expects(index != 0);
        segment_descriptor_type sd1 = m_gdt.at(index);

        // The segment limit description can be found in the Intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // ------------------------------------------------------------------
        // |               | Limit 19-16 |                                  |
        // ------------------------------------------------------------------
        // |                             |            Limit 15-00           |
        // ------------------------------------------------------------------

        if ((sd1 & 0x80000000000000) != 0)
        {
            limit_type limit_15_00 = gsl::narrow_cast<limit_type>((sd1 & 0x000000000000FFFF) >> 0);
            limit_type limit_19_16 = gsl::narrow_cast<limit_type>((sd1 & 0x000F000000000000) >> 32);

            return ((limit_19_16 | limit_15_00) << 12) | 0x0000000000000FFF;
        }

        limit_type limit_15_00 = gsl::narrow_cast<limit_type>((sd1 & 0x000000000000FFFF) >> 0);
        limit_type limit_19_16 = gsl::narrow_cast<limit_type>((sd1 & 0x000F000000000000) >> 32);

        return limit_19_16 | limit_15_00;
    }

    void set_access_rights(index_type index, access_rights_type access_rights)
    {
        expects(index != 0);
        segment_descriptor_type sd1 = (m_gdt.at(index) & 0xFF0F00FFFFFFFFFF);

        // The segment access description can be found in the intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // ------------------------------------------------------------------
        // |           | A 15-12 |       |  Access 07-00   |                |
        // ------------------------------------------------------------------
        // |                             |                                  |
        // ------------------------------------------------------------------
        //

        segment_descriptor_type access_rights_07_00 = ((static_cast<segment_descriptor_type>(access_rights) & 0x00000000000000FF) << 40);
        segment_descriptor_type access_rights_15_12 = ((static_cast<segment_descriptor_type>(access_rights) & 0x000000000000F000) << 40);

        m_gdt.at(index) = sd1 | access_rights_15_12 | access_rights_07_00;
    }

    access_rights_type access_rights(index_type index) const
    {
        expects(index != 0);
        segment_descriptor_type sd1 = m_gdt.at(index);

        // The segment access description can be found in the Intel's software
        // developer's manual, volume 3, chapter 3.4.5 as well as volume 3,
        // chapter 24.4.1.
        //
        // ------------------------------------------------------------------
        // |           | A 15-12 |       |  Access 07-00   |                |
        // ------------------------------------------------------------------
        // |                             |                                  |
        // ------------------------------------------------------------------
        //

        access_rights_type access_rights_07_00 = static_cast<access_rights_type>((sd1 & 0x0000FF0000000000) >> 40);
        access_rights_type access_rights_15_12 = static_cast<access_rights_type>((sd1 & 0x00F0000000000000) >> 40);

        return access_rights_15_12 | access_rights_07_00;
    }

private:

    friend class intrinsics_ut;

    gdt_reg_x64_t m_gdt_reg;
    std::vector<segment_descriptor_type> m_gdt;
};

#endif