vmcs_intel_x64_32bit_read_only_data_fields.h File Reference

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Namespaces
	intel_x64
	intel_x64::vmcs
	intel_x64::vmcs::vm_instruction_error
	intel_x64::vmcs::exit_reason
	intel_x64::vmcs::exit_reason::basic_exit_reason
	intel_x64::vmcs::exit_reason::reserved
	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode
	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit
	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation
	intel_x64::vmcs::exit_reason::vm_entry_failure
	intel_x64::vmcs::vm_exit_interruption_information
	intel_x64::vmcs::vm_exit_interruption_information::vector
	intel_x64::vmcs::vm_exit_interruption_information::interruption_type
	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid
	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret
	intel_x64::vmcs::vm_exit_interruption_information::reserved
	intel_x64::vmcs::vm_exit_interruption_information::valid_bit
	intel_x64::vmcs::vm_exit_interruption_error_code
	intel_x64::vmcs::idt_vectoring_information
	intel_x64::vmcs::idt_vectoring_information::vector
	intel_x64::vmcs::idt_vectoring_information::interruption_type
	intel_x64::vmcs::idt_vectoring_information::error_code_valid
	intel_x64::vmcs::idt_vectoring_information::reserved
	intel_x64::vmcs::idt_vectoring_information::valid_bit
	intel_x64::vmcs::idt_vectoring_error_code
	intel_x64::vmcs::vm_exit_instruction_length
	intel_x64::vmcs::vm_exit_instruction_information
	intel_x64::vmcs::vm_exit_instruction_information::ins
	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size
	intel_x64::vmcs::vm_exit_instruction_information::outs
	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size
	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::invept
	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling
	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size
	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2
	intel_x64::vmcs::vm_exit_instruction_information::invpcid
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2
	intel_x64::vmcs::vm_exit_instruction_information::invvpid
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2
	intel_x64::vmcs::vm_exit_instruction_information::lidt
	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::lgdt
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::sidt
	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::sgdt
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::lldt
	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1
	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::ltr
	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling
	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1
	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size
	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::sldt
	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling
	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1
	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size
	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::str
	intel_x64::vmcs::vm_exit_instruction_information::str::scaling
	intel_x64::vmcs::vm_exit_instruction_information::str::reg1
	intel_x64::vmcs::vm_exit_instruction_information::str::address_size
	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity
	intel_x64::vmcs::vm_exit_instruction_information::rdrand
	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register
	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::rdseed
	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register
	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size
	intel_x64::vmcs::vm_exit_instruction_information::vmclear
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmxon
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::xrstors
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::xsaves
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmread
	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1
	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid
	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2

Functions
auto	intel_x64::vmcs::vm_instruction_error::exists () noexcept
auto	intel_x64::vmcs::vm_instruction_error::get ()
auto	intel_x64::vmcs::vm_instruction_error::get_if_exists (bool verbose=false) noexcept
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::vm_instruction_error::__vm_instruction_error_description (T error)
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::vm_instruction_error::vm_instruction_error_description (T error, bool exists)
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::vm_instruction_error::vm_instruction_error_description_if_exists (T error, bool verbose, bool exists)
auto	intel_x64::vmcs::vm_instruction_error::description ()
auto	intel_x64::vmcs::vm_instruction_error::description_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::exit_reason::exists () noexcept
auto	intel_x64::vmcs::exit_reason::get ()
auto	intel_x64::vmcs::exit_reason::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::get ()
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::get_if_exists (bool verbose=false) noexcept
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::__basic_exit_reason_description (T reason)
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::basic_exit_reason_description (T reason, bool exists)
template<class T , class = typename std::enable_if<std::is_integral<T>::value>::type>
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::basic_exit_reason_description_if_exists (T reason, bool verbose, bool exists)
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::description ()
auto	intel_x64::vmcs::exit_reason::basic_exit_reason::description_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::exit_reason::reserved::get ()
auto	intel_x64::vmcs::exit_reason::reserved::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::is_enabled ()
auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::is_enabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::is_disabled ()
auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::is_disabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::is_enabled ()
auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::is_enabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::is_disabled ()
auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::is_disabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::is_enabled ()
auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::is_enabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::is_disabled ()
auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::is_disabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::vm_entry_failure::is_enabled ()
auto	intel_x64::vmcs::exit_reason::vm_entry_failure::is_enabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::exit_reason::vm_entry_failure::is_disabled ()
auto	intel_x64::vmcs::exit_reason::vm_entry_failure::is_disabled_if_exists (bool verbose=false)
auto	intel_x64::vmcs::vm_exit_interruption_information::exists () noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::get ()
auto	intel_x64::vmcs::vm_exit_interruption_information::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::vector::get ()
auto	intel_x64::vmcs::vm_exit_interruption_information::vector::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::get ()
auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::is_enabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::is_enabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::is_disabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::is_disabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::is_enabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::is_enabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::is_disabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::is_disabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::reserved::get ()
auto	intel_x64::vmcs::vm_exit_interruption_information::reserved::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::is_enabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::is_enabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::is_disabled ()
auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::is_disabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_interruption_error_code::exists () noexcept
auto	intel_x64::vmcs::vm_exit_interruption_error_code::get ()
auto	intel_x64::vmcs::vm_exit_interruption_error_code::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::exists () noexcept
auto	intel_x64::vmcs::idt_vectoring_information::get ()
auto	intel_x64::vmcs::idt_vectoring_information::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::vector::get ()
auto	intel_x64::vmcs::idt_vectoring_information::vector::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::get ()
auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::is_enabled ()
auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::is_enabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::is_disabled ()
auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::is_disabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::reserved::get ()
auto	intel_x64::vmcs::idt_vectoring_information::reserved::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::is_enabled ()
auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::is_enabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::is_disabled ()
auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::is_disabled_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::idt_vectoring_error_code::exists () noexcept
auto	intel_x64::vmcs::idt_vectoring_error_code::get ()
auto	intel_x64::vmcs::idt_vectoring_error_code::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_length::exists () noexcept
auto	intel_x64::vmcs::vm_exit_instruction_length::get ()
auto	intel_x64::vmcs::vm_exit_instruction_length::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::exists () noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ins::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ins::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ins::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::get_name ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::get_if_exists (bool verbose=false) noexcept
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::get ()
auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::get_if_exists (bool verbose=false) noexcept

Variables
constexpr const auto	intel_x64::vmcs::vm_instruction_error::addr = 0x0000000000004400UL
constexpr const auto	intel_x64::vmcs::vm_instruction_error::name = "vm_instruction_error"
constexpr const auto	intel_x64::vmcs::exit_reason::addr = 0x0000000000004402UL
constexpr const auto	intel_x64::vmcs::exit_reason::name = "exit_reason"
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::mask = 0x000000000000FFFFUL
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::from = 0
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::name = "basic_exit_reason"
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::exception_or_non_maskable_interrupt = 0U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::external_interrupt = 1U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::triple_fault = 2U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::init_signal = 3U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::sipi = 4U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::smi = 5U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::other_smi = 6U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::interrupt_window = 7U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::nmi_window = 8U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::task_switch = 9U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::cpuid = 10U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::getsec = 11U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::hlt = 12U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::invd = 13U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::invlpg = 14U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdpmc = 15U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdtsc = 16U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rsm = 17U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmcall = 18U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmclear = 19U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmlaunch = 20U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmptrld = 21U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmptrst = 22U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmread = 23U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmresume = 24U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmwrite = 25U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmxoff = 26U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmxon = 27U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::control_register_accesses = 28U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::mov_dr = 29U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::io_instruction = 30U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdmsr = 31U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::wrmsr = 32U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vm_entry_failure_invalid_guest_state = 33U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vm_entry_failure_msr_loading = 34U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::mwait = 36U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::monitor_trap_flag = 37U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::monitor = 39U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::pause = 40U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vm_entry_failure_machine_check_event = 41U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::tpr_below_threshold = 43U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::apic_access = 44U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::virtualized_eoi = 45U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::access_to_gdtr_or_idtr = 46U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::access_to_ldtr_or_tr = 47U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::ept_violation = 48U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::ept_misconfiguration = 49U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::invept = 50U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdtscp = 51U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmx_preemption_timer_expired = 52U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::invvpid = 53U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::wbinvd = 54U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::xsetbv = 55U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::apic_write = 56U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdrand = 57U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::invpcid = 58U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::vmfunc = 59U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::rdseed = 61U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::xsaves = 63U
constexpr const auto	intel_x64::vmcs::exit_reason::basic_exit_reason::xrstors = 64U
constexpr const auto	intel_x64::vmcs::exit_reason::reserved::mask = 0x0000000047FF0000UL
constexpr const auto	intel_x64::vmcs::exit_reason::reserved::from = 0
constexpr const auto	intel_x64::vmcs::exit_reason::reserved::name = "reserved"
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::from = 27
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_incident_to_enclave_mode::name = "vm_exit_incident_to_enclave_mode"
constexpr const auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::mask = 0x0000000010000000UL
constexpr const auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::from = 28
constexpr const auto	intel_x64::vmcs::exit_reason::pending_mtf_vm_exit::name = "pending_mtf_vm_exit"
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::mask = 0x0000000020000000UL
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::from = 29
constexpr const auto	intel_x64::vmcs::exit_reason::vm_exit_from_vmx_root_operation::name = "vm_exit_from_vmx_root_operation"
constexpr const auto	intel_x64::vmcs::exit_reason::vm_entry_failure::mask = 0x0000000080000000UL
constexpr const auto	intel_x64::vmcs::exit_reason::vm_entry_failure::from = 31
constexpr const auto	intel_x64::vmcs::exit_reason::vm_entry_failure::name = "vm_entry_failure"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::addr = 0x0000000000004404UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::name = "vm_exit_interruption_information"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::vector::mask = 0x000000FFUL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::vector::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::vector::name = "vector"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::mask = 0x00000700UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::from = 8
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::name = "interruption_type"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::external_interrupt = 0UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::non_maskable_interrupt = 2UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::hardware_exception = 3UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::interruption_type::software_exception = 6UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::mask = 0x00000800UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::error_code_valid::name = "deliver_error_code_bit"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::mask = 0x00001000UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::from = 12
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::nmi_unblocking_due_to_iret::name = "nmi_unblocking_due_to_iret"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::reserved::mask = 0x7FFFE000UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::reserved::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::reserved::name = "reserved"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::mask = 0x80000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::from = 31
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_information::valid_bit::name = "valid_bit"
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_error_code::addr = 0x0000000000004406UL
constexpr const auto	intel_x64::vmcs::vm_exit_interruption_error_code::name = "vm_exit_interruption_error_code"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::addr = 0x0000000000004408UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::name = "idt_vectoring_information_field"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::vector::mask = 0x000000FFUL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::vector::from = 0
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::vector::name = "vector"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::mask = 0x00000700UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::from = 8
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::name = "interruption_type"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::external_interrupt = 0UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::non_maskable_interrupt = 2UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::hardware_exception = 3UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::software_interrupt = 4UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::privileged_software_exception = 5UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::interruption_type::software_exception = 6UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::mask = 0x00000800UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::from = 11
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::error_code_valid::name = "deliver_error_code_bit"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::reserved::mask = 0x7FFFE000UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::reserved::from = 0
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::reserved::name = "reserved"
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::mask = 0x80000000UL
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::from = 31
constexpr const auto	intel_x64::vmcs::idt_vectoring_information::valid_bit::name = "valid_bit"
constexpr const auto	intel_x64::vmcs::idt_vectoring_error_code::addr = 0x000000000000440AUL
constexpr const auto	intel_x64::vmcs::idt_vectoring_error_code::name = "idt_vectoring_error_code"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_length::addr = 0x000000000000440CUL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_length::name = "vm_exit_instruction_length"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::addr = 0x000000000000440EUL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::name = "vm_exit_instruction_information"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::name = "ins"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ins::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::name = "outs"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::outs::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::name = "invept"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::mask = 0x00000000F0000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::name = "reg2"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invept::reg2::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::name = "invpcid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::mask = 0x00000000F0000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::name = "reg2"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invpcid::reg2::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::name = "invvpid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::mask = 0x00000000F0000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::name = "reg2"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::invvpid::reg2::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::name = "lidt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::mask = 0x0000000000000800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::sgdt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::sidt = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::lgdt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lidt::instruction_identity::lidt = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::name = "lgdt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::mask = 0x0000000000000800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::sgdt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::sidt = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::lgdt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lgdt::instruction_identity::lidt = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::name = "sidt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::mask = 0x0000000000000800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::sgdt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::sidt = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::lgdt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sidt::instruction_identity::lidt = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::name = "sgdt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::mask = 0x0000000000000800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::sgdt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::sidt = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::lgdt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sgdt::instruction_identity::lidt = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::name = "lldt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::sldt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::str = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::lldt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::lldt::instruction_identity::ltr = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::name = "ltr"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::sldt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::str = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::lldt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::ltr::instruction_identity::ltr = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::name = "sldt"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::sldt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::str = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::lldt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::sldt::instruction_identity::ltr = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::name = "str"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::mask = 0x0000000030000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::name = "instruction_identity"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::sldt = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::str = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::lldt = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::str::instruction_identity::ltr = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::name = "rdrand"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::name = "destination_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::destination_register::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::mask = 0x0000000000001800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdrand::operand_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::name = "rdseed"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::name = "destination_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::destination_register::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::mask = 0x0000000000001800UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::from = 11
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::name = "operand_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::rdseed::operand_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::name = "vmclear"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmclear::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::name = "vmptrld"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrld::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::name = "vmptrst"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmptrst::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::name = "vmxon"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmxon::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::name = "xrstors"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xrstors::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::name = "xsaves"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::xsaves::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::name = "vmread"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::mask = 0x00000000F0000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::name = "reg2"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmread::reg2::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::name = "vmwrite"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::mask = 0x0000000000000003UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::from = 0
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::name = "scaling"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::no_scaling = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::scale_by_2 = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::scale_by_4 = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::scaling::scale_by_8 = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::mask = 0x0000000000000078UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::from = 3
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::name = "reg1"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg1::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::mask = 0x0000000000000380UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::from = 7
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::name = "address_size"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::_16bit = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::_32bit = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::address_size::_64bit = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::mask = 0x0000000000000400UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::from = 10
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::name = "mem/reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::mem = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::mem_reg::reg = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::mask = 0x0000000000038000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::from = 15
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::name = "segment_register"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::es = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::cs = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::ss = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::ds = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::fs = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::segment_register::gs = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::mask = 0x00000000003C0000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::from = 18
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::name = "index_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::mask = 0x0000000000400000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::from = 22
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::name = "index_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::index_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::mask = 0x0000000007800000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::from = 23
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::name = "base_reg"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg::r15 = 15U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::mask = 0x0000000008000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::from = 27
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::name = "base_reg_invalid"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::valid = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::base_reg_invalid::invalid = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::mask = 0x00000000F0000000UL
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::from = 28
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::name = "reg2"
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rax = 0U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rcx = 1U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rdx = 2U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rbx = 3U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rsp = 4U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rbp = 5U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rsi = 6U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::rdi = 7U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r8 = 8U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r9 = 9U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r10 = 10U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r11 = 11U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r12 = 12U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r13 = 13U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r14 = 14U
constexpr const auto	intel_x64::vmcs::vm_exit_instruction_information::vmwrite::reg2::r15 = 15U