test_msrs_intel_x64.cpp
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1 //
2 // Bareflank Hypervisor
3 //
4 // Copyright (C) 2015 Assured Information Security, Inc.
5 // Author: Rian Quinn <quinnr@ainfosec.com>
6 // Author: Brendan Kerrigan <kerriganb@ainfosec.com>
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2.1 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 
22 #include <test.h>
24 
25 using namespace intel_x64;
26 
27 extern std::map<msrs::field_type, msrs::value_type> g_msrs;
28 
29 void
30 intrinsics_ut::test_general_msr_access()
31 {
32  msrs::set(0x1, 100UL);
33  this->expect_true(msrs::get(0x1) == 100UL);
34 }
35 
36 void
37 intrinsics_ut::test_ia32_feature_control()
38 {
39  msrs::ia32_feature_control::set(0xFFFFFFFFFFFFFFFFUL);
40  this->expect_true(msrs::ia32_feature_control::get() == 0xFFFFFFFFFFFFFFFFUL);
41 
43 
46 }
47 
48 void
49 intrinsics_ut::test_ia32_feature_control_lock_bit()
50 {
53 
56 }
57 
58 void
59 intrinsics_ut::test_ia32_feature_control_enable_vmx_inside_smx()
60 {
63 
66 }
67 
68 void
69 intrinsics_ut::test_ia32_feature_control_enable_vmx_outside_smx()
70 {
73 
76 }
77 
78 void
79 intrinsics_ut::test_ia32_feature_control_senter_local_function_enables()
80 {
83 
86 }
87 
88 void
89 intrinsics_ut::test_ia32_feature_control_senter_gloabl_function_enable()
90 {
93 
96 }
97 
98 void
99 intrinsics_ut::test_ia32_feature_control_sgx_launch_control_enable()
100 {
103 
106 }
107 
108 void
109 intrinsics_ut::test_ia32_feature_control_sgx_global_enable()
110 {
113 
116 }
117 
118 void
119 intrinsics_ut::test_ia32_feature_control_lmce()
120 {
123 
126 }
127 
128 void
129 intrinsics_ut::test_ia32_sysenter_cs()
130 {
132  this->expect_true(msrs::ia32_sysenter_cs::get() == 100UL);
133 }
134 
135 void
136 intrinsics_ut::test_ia32_sysenter_esp()
137 {
139  this->expect_true(msrs::ia32_sysenter_esp::get() == 100UL);
140 }
141 
142 void
143 intrinsics_ut::test_ia32_sysenter_eip()
144 {
146  this->expect_true(msrs::ia32_sysenter_eip::get() == 100UL);
147 }
148 
149 void
150 intrinsics_ut::test_ia32_debugctl()
151 {
152  msrs::ia32_debugctl::set(0xFFFFFFFFFFFFFFFFUL);
153  this->expect_true(msrs::ia32_debugctl::get() == 0xFFFFFFFFFFFFFFFFUL);
154 
156 
158  this->expect_true(msrs::ia32_debugctl::get() == 0x0U);
159 }
160 
161 void
162 intrinsics_ut::test_ia32_debugctl_lbr()
163 {
166 
169 }
170 
171 void
172 intrinsics_ut::test_ia32_debugctl_btf()
173 {
176 
179 }
180 
181 void
182 intrinsics_ut::test_ia32_debugctl_tr()
183 {
186 
189 }
190 
191 void
192 intrinsics_ut::test_ia32_debugctl_bts()
193 {
196 
199 }
200 
201 void
202 intrinsics_ut::test_ia32_debugctl_btint()
203 {
206 
209 }
210 
211 void
212 intrinsics_ut::test_ia32_debugctl_bt_off_os()
213 {
216 
219 }
220 
221 void
222 intrinsics_ut::test_ia32_debugctl_bt_off_user()
223 {
226 
229 }
230 
231 void
232 intrinsics_ut::test_ia32_debugctl_freeze_lbrs_on_pmi()
233 {
236 
239 }
240 
241 void
242 intrinsics_ut::test_ia32_debugctl_freeze_perfmon_on_pmi()
243 {
246 
249 }
250 
251 void
252 intrinsics_ut::test_ia32_debugctl_enable_uncore_pmi()
253 {
256 
259 }
260 
261 void
262 intrinsics_ut::test_ia32_debugctl_freeze_while_smm()
263 {
266 
269 }
270 
271 void
272 intrinsics_ut::test_ia32_debugctl_rtm_debug()
273 {
276 
279 }
280 
281 void
282 intrinsics_ut::test_ia32_debugctl_reserved()
283 {
284  msrs::ia32_debugctl::reserved::set(0x100000000UL);
285  this->expect_true(msrs::ia32_debugctl::reserved::get() == 0x100000000UL);
286 }
287 
288 void
289 intrinsics_ut::test_ia32_perf_global_ctrl()
290 {
291  msrs::ia32_perf_global_ctrl::set(0xFFFFFFFFFFFFFFFFUL);
292  this->expect_true(msrs::ia32_perf_global_ctrl::get() == 0xFFFFFFFFFFFFFFFFUL);
293 
295 
298 }
299 
300 void
301 intrinsics_ut::test_ia32_perf_global_ctrl_pmc0()
302 {
305 
308 }
309 
310 void
311 intrinsics_ut::test_ia32_perf_global_ctrl_pmc1()
312 {
315 
318 }
319 
320 void
321 intrinsics_ut::test_ia32_perf_global_ctrl_pmc2()
322 {
325 
328 }
329 
330 void
331 intrinsics_ut::test_ia32_perf_global_ctrl_pmc3()
332 {
335 
338 }
339 
340 void
341 intrinsics_ut::test_ia32_perf_global_ctrl_pmc4()
342 {
345 
348 }
349 
350 void
351 intrinsics_ut::test_ia32_perf_global_ctrl_pmc5()
352 {
355 
358 }
359 
360 void
361 intrinsics_ut::test_ia32_perf_global_ctrl_pmc6()
362 {
365 
368 }
369 
370 void
371 intrinsics_ut::test_ia32_perf_global_ctrl_pmc7()
372 {
375 
378 }
379 
380 void
381 intrinsics_ut::test_ia32_perf_global_ctrl_fixed_ctr0()
382 {
385 
388 }
389 
390 void
391 intrinsics_ut::test_ia32_perf_global_ctrl_fixed_ctr1()
392 {
395 
398 }
399 
400 void
401 intrinsics_ut::test_ia32_perf_global_ctrl_fixed_ctr2()
402 {
405 
408 }
409 
410 void
411 intrinsics_ut::test_ia32_vmx_basic()
412 {
413  g_msrs[msrs::ia32_vmx_basic::addr] = 0xFFFFFFFFFFFFFFFFUL;
414  this->expect_true(msrs::ia32_vmx_basic::get() == 0xFFFFFFFFFFFFFFFFUL);
415 
417 
419  this->expect_true(msrs::ia32_vmx_basic::get() == 0x0U);
420 }
421 
422 void
423 intrinsics_ut::test_ia32_vmx_basic_revision_id()
424 {
427 
430 }
431 
432 void
433 intrinsics_ut::test_ia32_vmx_basic_vmxon_vmcs_region_size()
434 {
437 
440 }
441 
442 void
443 intrinsics_ut::test_ia32_vmx_basic_physical_address_width()
444 {
446 
449 
452 }
453 
454 void
455 intrinsics_ut::test_ia32_vmx_basic_dual_monitor_mode_support()
456 {
458 
461 
464 }
465 
466 void
467 intrinsics_ut::test_ia32_vmx_basic_memory_type()
468 {
471 
474 }
475 
476 void
477 intrinsics_ut::test_ia32_vmx_basic_ins_outs_exit_information()
478 {
480 
483 
486 }
487 
488 void
489 intrinsics_ut::test_ia32_vmx_basic_true_based_controls()
490 {
492 
495 
498 }
499 
500 void
501 intrinsics_ut::test_ia32_vmx_misc()
502 {
503  g_msrs[msrs::ia32_vmx_misc::addr] = 0xFFFFFFFFFFFFFFFFUL;
504  this->expect_true(msrs::ia32_vmx_misc::get() == 0xFFFFFFFFFFFFFFFFUL);
505 
507 
509  this->expect_true(msrs::ia32_vmx_misc::get() == 0x0U);
510 }
511 
512 void
513 intrinsics_ut::test_ia32_vmx_misc_preemption_timer_decrement()
514 {
517 
520 }
521 
522 void
523 intrinsics_ut::test_ia32_vmx_misc_store_efer_lma_on_vm_exit()
524 {
526 
529 
532 }
533 
534 void
535 intrinsics_ut::test_ia32_vmx_misc_activity_state_hlt_support()
536 {
538 
541 
544 }
545 
546 void
547 intrinsics_ut::test_ia32_vmx_misc_activity_state_shutdown_support()
548 {
550 
553 
556 }
557 
558 void
559 intrinsics_ut::test_ia32_vmx_misc_activity_state_wait_for_sipi_support()
560 {
562 
565 
568 }
569 
570 void
571 intrinsics_ut::test_ia32_vmx_misc_processor_trace_support()
572 {
574 
577 
580 }
581 
582 void
583 intrinsics_ut::test_ia32_vmx_misc_rdmsr_in_smm_support()
584 {
586 
589 
592 }
593 
594 void
595 intrinsics_ut::test_ia32_vmx_misc_cr3_targets()
596 {
599 
602 }
603 
604 void
605 intrinsics_ut::test_ia32_vmx_misc_max_num_msr_load_store_on_exit()
606 {
609 
612 }
613 
614 void
615 intrinsics_ut::test_ia32_vmx_misc_vmxoff_blocked_smi_support()
616 {
618 
621 
624 }
625 
626 void
627 intrinsics_ut::test_ia32_vmx_misc_vmwrite_all_fields_support()
628 {
630 
633 
636 }
637 
638 void
639 intrinsics_ut::test_ia32_vmx_misc_injection_with_instruction_length_of_zero()
640 {
642 
645 
648 }
649 
650 void
651 intrinsics_ut::test_ia32_vmx_cr0_fixed0()
652 {
653  g_msrs[msrs::ia32_vmx_cr0_fixed0::addr] = 0xFFFFFFFFFFFFFFFFUL;
654  this->expect_true(msrs::ia32_vmx_cr0_fixed0::get() == 0xFFFFFFFFFFFFFFFFUL);
655 
658 }
659 
660 void
661 intrinsics_ut::test_ia32_vmx_cr0_fixed1()
662 {
663  g_msrs[msrs::ia32_vmx_cr0_fixed1::addr] = 0xFFFFFFFFFFFFFFFFUL;
664  this->expect_true(msrs::ia32_vmx_cr0_fixed1::get() == 0xFFFFFFFFFFFFFFFFUL);
665 
668 }
669 
670 void
671 intrinsics_ut::test_ia32_vmx_cr4_fixed0()
672 {
673  g_msrs[msrs::ia32_vmx_cr4_fixed0::addr] = 0xFFFFFFFFFFFFFFFFUL;
674  this->expect_true(msrs::ia32_vmx_cr4_fixed0::get() == 0xFFFFFFFFFFFFFFFFUL);
675 
678 }
679 
680 void
681 intrinsics_ut::test_ia32_vmx_cr4_fixed1()
682 {
683  g_msrs[msrs::ia32_vmx_cr4_fixed1::addr] = 0xFFFFFFFFFFFFFFFFUL;
684  this->expect_true(msrs::ia32_vmx_cr4_fixed1::get() == 0xFFFFFFFFFFFFFFFFUL);
685 
688 }
689 
690 void
691 intrinsics_ut::test_ia32_vmx_procbased_ctls2()
692 {
693  g_msrs[msrs::ia32_vmx_procbased_ctls2::addr] = 0x00000000FFFFFFFFUL;
694  this->expect_true(msrs::ia32_vmx_procbased_ctls2::get() == 0x00000000FFFFFFFFUL);
695 
697 
700 
702 
703  g_msrs[msrs::ia32_vmx_procbased_ctls2::addr] = 0x00000000FFFFFFFFUL;
706 
708 
709  g_msrs[msrs::ia32_vmx_procbased_ctls2::addr] = 0xFFFFFFFF00000000U;
712 
714 }
715 
716 void
717 intrinsics_ut::test_ia32_vmx_procbased_ctls2_virtualize_apic_accesses()
718 {
720 
723 
726 
730 
734 }
735 
736 void
737 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_ept()
738 {
740 
743 
746 
750 
754 }
755 
756 void
757 intrinsics_ut::test_ia32_vmx_procbased_ctls2_descriptor_table_exiting()
758 {
760 
763 
766 
770 
774 }
775 
776 void
777 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_rdtscp()
778 {
780 
783 
786 
790 
794 }
795 
796 void
797 intrinsics_ut::test_ia32_vmx_procbased_ctls2_virtualize_x2apic_mode()
798 {
800 
803 
806 
810 
814 }
815 
816 void
817 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_vpid()
818 {
820 
823 
826 
830 
834 }
835 
836 void
837 intrinsics_ut::test_ia32_vmx_procbased_ctls2_wbinvd_exiting()
838 {
840 
843 
846 
850 
854 }
855 
856 void
857 intrinsics_ut::test_ia32_vmx_procbased_ctls2_unrestricted_guest()
858 {
860 
863 
866 
870 
874 }
875 
876 void
877 intrinsics_ut::test_ia32_vmx_procbased_ctls2_apic_register_virtualization()
878 {
880 
883 
886 
890 
894 }
895 
896 void
897 intrinsics_ut::test_ia32_vmx_procbased_ctls2_virtual_interrupt_delivery()
898 {
900 
903 
906 
910 
914 }
915 
916 void
917 intrinsics_ut::test_ia32_vmx_procbased_ctls2_pause_loop_exiting()
918 {
920 
923 
926 
930 
934 }
935 
936 void
937 intrinsics_ut::test_ia32_vmx_procbased_ctls2_rdrand_exiting()
938 {
940 
943 
946 
950 
954 }
955 
956 void
957 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_invpcid()
958 {
960 
963 
966 
970 
974 }
975 
976 void
977 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_vm_functions()
978 {
980 
983 
986 
990 
994 }
995 
996 void
997 intrinsics_ut::test_ia32_vmx_procbased_ctls2_vmcs_shadowing()
998 {
1000 
1003 
1006 
1010 
1014 }
1015 
1016 void
1017 intrinsics_ut::test_ia32_vmx_procbased_ctls2_rdseed_exiting()
1018 {
1020 
1023 
1026 
1030 
1034 }
1035 
1036 void
1037 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_pml()
1038 {
1040 
1043 
1046 
1050 
1054 }
1055 
1056 void
1057 intrinsics_ut::test_ia32_vmx_procbased_ctls2_ept_violation_ve()
1058 {
1060 
1063 
1066 
1070 
1074 }
1075 
1076 void
1077 intrinsics_ut::test_ia32_vmx_procbased_ctls2_enable_xsaves_xrstors()
1078 {
1080 
1083 
1086 
1090 
1094 }
1095 
1096 void
1097 intrinsics_ut::test_ia32_vmx_ept_vpid_cap()
1098 {
1099  g_msrs[msrs::ia32_vmx_ept_vpid_cap::addr] = 0xFFFFFFFFFFFFFFFFUL;
1100  this->expect_true(msrs::ia32_vmx_ept_vpid_cap::get() == 0xFFFFFFFFFFFFFFFFUL);
1101 
1103 
1106 }
1107 
1108 void
1109 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_execute_only_translation()
1110 {
1112 
1115 
1118 }
1119 
1120 void
1121 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_page_walk_length_of_4()
1122 {
1124 
1127 
1130 }
1131 
1132 void
1133 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_memory_type_uncacheable_supported()
1134 {
1136 
1139 
1142 }
1143 
1144 void
1145 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_memory_type_write_back_supported()
1146 {
1148 
1151 
1154 }
1155 
1156 void
1157 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_pde_2mb_support()
1158 {
1160 
1163 
1166 }
1167 
1168 void
1169 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_pdpte_1gb_support()
1170 {
1172 
1175 
1178 }
1179 
1180 void
1181 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invept_support()
1182 {
1184 
1187 
1190 }
1191 
1192 void
1193 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_accessed_dirty_support()
1194 {
1196 
1199 
1202 }
1203 
1204 void
1205 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invept_single_context_support()
1206 {
1208 
1211 
1214 }
1215 
1216 void
1217 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invept_all_context_support()
1218 {
1220 
1223 
1226 }
1227 
1228 void
1229 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invvpid_support()
1230 {
1232 
1235 
1238 }
1239 
1240 void
1241 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invvpid_individual_address_support()
1242 {
1244 
1247 
1250 }
1251 
1252 void
1253 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invvpid_single_context_support()
1254 {
1256 
1259 
1262 }
1263 
1264 void
1265 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invvpid_all_context_support()
1266 {
1268 
1271 
1274 }
1275 
1276 void
1277 intrinsics_ut::test_ia32_vmx_ept_vpid_cap_invvpid_single_context_retaining_globals_support()
1278 {
1280 
1283 
1286 }
1287 
1288 void
1289 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls()
1290 {
1291  g_msrs[msrs::ia32_vmx_true_pinbased_ctls::addr] = 0x00000000FFFFFFFFUL;
1292  this->expect_true(msrs::ia32_vmx_true_pinbased_ctls::get() == 0x00000000FFFFFFFFUL);
1293 
1295 
1298 
1300 
1301  g_msrs[msrs::ia32_vmx_true_pinbased_ctls::addr] = 0x00000000FFFFFFFFUL;
1304 
1306 
1307  g_msrs[msrs::ia32_vmx_true_pinbased_ctls::addr] = 0xFFFFFFFF00000000U;
1310 
1312 }
1313 
1314 void
1315 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls_external_interrupt_exiting()
1316 {
1318 
1321 
1324 
1328 
1332 }
1333 
1334 void
1335 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls_nmi_exiting()
1336 {
1338 
1341 
1344 
1348 
1352 }
1353 
1354 void
1355 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls_virtual_nmis()
1356 {
1358 
1361 
1364 
1368 
1372 }
1373 
1374 void
1375 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls_activate_vmx_preemption_timer()
1376 {
1378 
1381 
1384 
1388 
1392 }
1393 
1394 void
1395 intrinsics_ut::test_ia32_vmx_true_pinbased_ctls_process_posted_interrupts()
1396 {
1398 
1401 
1404 
1408 
1412 }
1413 
1414 void
1415 intrinsics_ut::test_ia32_vmx_true_procbased_ctls()
1416 {
1417  g_msrs[msrs::ia32_vmx_true_procbased_ctls::addr] = 0x00000000FFFFFFFFUL;
1418  this->expect_true(msrs::ia32_vmx_true_procbased_ctls::get() == 0x00000000FFFFFFFFUL);
1419 
1421 
1424 
1426 
1427  g_msrs[msrs::ia32_vmx_true_procbased_ctls::addr] = 0x00000000FFFFFFFFUL;
1430 
1432 
1433  g_msrs[msrs::ia32_vmx_true_procbased_ctls::addr] = 0xFFFFFFFF00000000U;
1436 
1438 }
1439 
1440 void
1441 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_interrupt_window_exiting()
1442 {
1444 
1447 
1450 
1454 
1458 }
1459 
1460 void
1461 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_use_tsc_offsetting()
1462 {
1464 
1467 
1470 
1474 
1478 }
1479 
1480 void
1481 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_hlt_exiting()
1482 {
1484 
1487 
1490 
1494 
1498 }
1499 
1500 void
1501 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_invlpg_exiting()
1502 {
1504 
1507 
1510 
1514 
1518 }
1519 
1520 void
1521 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_mwait_exiting()
1522 {
1524 
1527 
1530 
1534 
1538 }
1539 
1540 void
1541 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_rdpmc_exiting()
1542 {
1544 
1547 
1550 
1554 
1558 }
1559 
1560 void
1561 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_rdtsc_exiting()
1562 {
1564 
1567 
1570 
1574 
1578 }
1579 
1580 void
1581 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_cr3_load_exiting()
1582 {
1584 
1587 
1590 
1594 
1598 }
1599 
1600 void
1601 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_cr3_store_exiting()
1602 {
1604 
1607 
1610 
1614 
1618 }
1619 
1620 void
1621 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_cr8_load_exiting()
1622 {
1624 
1627 
1630 
1634 
1638 }
1639 
1640 void
1641 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_cr8_store_exiting()
1642 {
1644 
1647 
1650 
1654 
1658 }
1659 
1660 void
1661 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_use_tpr_shadow()
1662 {
1664 
1667 
1670 
1674 
1678 }
1679 
1680 void
1681 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_nmi_window_exiting()
1682 {
1684 
1687 
1690 
1694 
1698 }
1699 
1700 void
1701 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_mov_dr_exiting()
1702 {
1704 
1707 
1710 
1714 
1718 }
1719 
1720 void
1721 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_unconditional_io_exiting()
1722 {
1724 
1727 
1730 
1734 
1738 }
1739 
1740 void
1741 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_use_io_bitmaps()
1742 {
1744 
1747 
1750 
1754 
1758 }
1759 
1760 void
1761 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_monitor_trap_flag()
1762 {
1764 
1767 
1770 
1774 
1778 }
1779 
1780 void
1781 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_use_msr_bitmap()
1782 {
1784 
1787 
1790 
1794 
1798 }
1799 
1800 void
1801 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_monitor_exiting()
1802 {
1804 
1807 
1810 
1814 
1818 }
1819 
1820 void
1821 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_pause_exiting()
1822 {
1824 
1827 
1830 
1834 
1838 }
1839 
1840 void
1841 intrinsics_ut::test_ia32_vmx_true_procbased_ctls_activate_secondary_controls()
1842 {
1844 
1847 
1850 
1854 
1858 }
1859 
1860 void
1861 intrinsics_ut::test_ia32_vmx_true_exit_ctls()
1862 {
1863  g_msrs[msrs::ia32_vmx_true_exit_ctls::addr] = 0x00000000FFFFFFFFUL;
1864  this->expect_true(msrs::ia32_vmx_true_exit_ctls::get() == 0x00000000FFFFFFFFUL);
1865 
1867 
1870 
1872 
1873  g_msrs[msrs::ia32_vmx_true_exit_ctls::addr] = 0x00000000FFFFFFFFUL;
1874  this->expect_true(msrs::ia32_vmx_true_exit_ctls::allowed0() == 0xFFFFFFFFU);
1875  this->expect_true(msrs::ia32_vmx_true_exit_ctls::allowed1() == 0x00000000U);
1876 
1878 
1879  g_msrs[msrs::ia32_vmx_true_exit_ctls::addr] = 0xFFFFFFFF00000000U;
1880  this->expect_true(msrs::ia32_vmx_true_exit_ctls::allowed0() == 0x00000000U);
1881  this->expect_true(msrs::ia32_vmx_true_exit_ctls::allowed1() == 0xFFFFFFFFU);
1882 
1884 }
1885 
1886 void
1887 intrinsics_ut::test_ia32_vmx_true_exit_ctls_save_debug_controls()
1888 {
1890 
1893 
1896 
1900 
1904 }
1905 
1906 void
1907 intrinsics_ut::test_ia32_vmx_true_exit_ctls_host_address_space_size()
1908 {
1910 
1913 
1916 
1920 
1924 }
1925 
1926 void
1927 intrinsics_ut::test_ia32_vmx_true_exit_ctls_load_ia32_perf_global_ctrl()
1928 {
1930 
1933 
1936 
1940 
1944 }
1945 
1946 void
1947 intrinsics_ut::test_ia32_vmx_true_exit_ctls_acknowledge_interrupt_on_exit()
1948 {
1950 
1953 
1956 
1960 
1964 }
1965 
1966 void
1967 intrinsics_ut::test_ia32_vmx_true_exit_ctls_save_ia32_pat()
1968 {
1970 
1973 
1976 
1980 
1984 }
1985 
1986 void
1987 intrinsics_ut::test_ia32_vmx_true_exit_ctls_load_ia32_pat()
1988 {
1990 
1993 
1996 
2000 
2004 }
2005 
2006 void
2007 intrinsics_ut::test_ia32_vmx_true_exit_ctls_save_ia32_efer()
2008 {
2010 
2013 
2016 
2020 
2024 }
2025 
2026 void
2027 intrinsics_ut::test_ia32_vmx_true_exit_ctls_load_ia32_efer()
2028 {
2030 
2033 
2036 
2040 
2044 }
2045 
2046 void
2047 intrinsics_ut::test_ia32_vmx_true_exit_ctls_save_vmx_preemption_timer_value()
2048 {
2050 
2053 
2056 
2060 
2064 }
2065 
2066 void
2067 intrinsics_ut::test_ia32_vmx_true_exit_ctls_clear_ia32_bndcfgs()
2068 {
2070 
2073 
2076 
2080 
2084 }
2085 
2086 void
2087 intrinsics_ut::test_ia32_vmx_true_entry_ctls()
2088 {
2089  g_msrs[msrs::ia32_vmx_true_entry_ctls::addr] = 0x00000000FFFFFFFFUL;
2090  this->expect_true(msrs::ia32_vmx_true_entry_ctls::get() == 0x00000000FFFFFFFFUL);
2091 
2093 
2096 
2098 
2099  g_msrs[msrs::ia32_vmx_true_entry_ctls::addr] = 0x00000000FFFFFFFFUL;
2100  this->expect_true(msrs::ia32_vmx_true_entry_ctls::allowed0() == 0xFFFFFFFFU);
2101  this->expect_true(msrs::ia32_vmx_true_entry_ctls::allowed1() == 0x00000000U);
2102 
2104 
2105  g_msrs[msrs::ia32_vmx_true_entry_ctls::addr] = 0xFFFFFFFF00000000U;
2106  this->expect_true(msrs::ia32_vmx_true_entry_ctls::allowed0() == 0x00000000U);
2107  this->expect_true(msrs::ia32_vmx_true_entry_ctls::allowed1() == 0xFFFFFFFFU);
2108 
2110 }
2111 
2112 void
2113 intrinsics_ut::test_ia32_vmx_true_entry_ctls_load_debug_controls()
2114 {
2116 
2119 
2122 
2126 
2130 }
2131 
2132 void
2133 intrinsics_ut::test_ia32_vmx_true_entry_ctls_ia_32e_mode_guest()
2134 {
2136 
2139 
2142 
2146 
2150 }
2151 
2152 void
2153 intrinsics_ut::test_ia32_vmx_true_entry_ctls_entry_to_smm()
2154 {
2156 
2159 
2162 
2166 
2170 }
2171 
2172 void
2173 intrinsics_ut::test_ia32_vmx_true_entry_ctls_deactivate_dual_monitor_treatment()
2174 {
2176 
2179 
2182 
2186 
2190 }
2191 
2192 void
2193 intrinsics_ut::test_ia32_vmx_true_entry_ctls_load_ia32_perf_global_ctrl()
2194 {
2196 
2199 
2202 
2206 
2210 }
2211 
2212 void
2213 intrinsics_ut::test_ia32_vmx_true_entry_ctls_load_ia32_pat()
2214 {
2216 
2219 
2222 
2226 
2230 }
2231 
2232 void
2233 intrinsics_ut::test_ia32_vmx_true_entry_ctls_load_ia32_efer()
2234 {
2236 
2239 
2242 
2246 
2250 }
2251 
2252 void
2253 intrinsics_ut::test_ia32_vmx_true_entry_ctls_load_ia32_bndcfgs()
2254 {
2256 
2259 
2262 
2266 
2270 }
2271 
2272 void
2273 intrinsics_ut::test_ia32_vmx_vmfunc()
2274 {
2275  g_msrs[msrs::ia32_vmx_vmfunc::addr] = 0xFFFFFFFFFFFFFFFFUL;
2276  this->expect_true(msrs::ia32_vmx_vmfunc::get() == 0xFFFFFFFFFFFFFFFFUL);
2277 
2279  this->expect_true(msrs::ia32_vmx_vmfunc::get() == 0x0U);
2280 }
2281 
2282 void
2283 intrinsics_ut::test_ia32_vmx_vmfunc_eptp_switching()
2284 {
2285  g_msrs[msrs::ia32_vmx_vmfunc::addr] = 0xFFFFFFFFFFFFFFFFUL;
2287 
2288  g_msrs[msrs::ia32_vmx_vmfunc::addr] = 0xFFFFFFFFFFFFFFFEUL;
2290 }
2291 
2292 void
2293 intrinsics_ut::test_ia32_efer()
2294 {
2295  msrs::ia32_efer::set(0xFFFFFFFFFFFFFFFFUL);
2296  this->expect_true(msrs::ia32_efer::get() == 0xFFFFFFFFFFFFFFFFUL);
2297 
2299 
2300  msrs::ia32_efer::set(0x0U);
2301  this->expect_true(msrs::ia32_efer::get() == 0x0U);
2302 }
2303 
2304 void
2305 intrinsics_ut::test_ia32_efer_sce()
2306 {
2309 
2312 }
2313 
2314 void
2315 intrinsics_ut::test_ia32_efer_lme()
2316 {
2319 
2322 }
2323 
2324 void
2325 intrinsics_ut::test_ia32_efer_lma()
2326 {
2329 
2332 }
2333 
2334 void
2335 intrinsics_ut::test_ia32_efer_nxe()
2336 {
2339 
2342 }
2343 
2344 void
2345 intrinsics_ut::test_ia32_efer_reserved()
2346 {
2347  msrs::ia32_efer::reserved::set(0x10000UL);
2348  this->expect_true(msrs::ia32_efer::reserved::get() == 0x10000UL);
2349 }
2350 
2351 void
2352 intrinsics_ut::test_ia32_fs_base()
2353 {
2354  msrs::ia32_fs_base::set(0xFFFFFFFFFFFFFFFFUL);
2355  this->expect_true(msrs::ia32_fs_base::get() == 0xFFFFFFFFFFFFFFFFUL);
2356 
2358  this->expect_true(msrs::ia32_fs_base::get() == 0x0U);
2359 }
2360 
2361 void
2362 intrinsics_ut::test_ia32_gs_base()
2363 {
2364  msrs::ia32_gs_base::set(0xFFFFFFFFFFFFFFFFUL);
2365  this->expect_true(msrs::ia32_gs_base::get() == 0xFFFFFFFFFFFFFFFFUL);
2366 
2368  this->expect_true(msrs::ia32_gs_base::get() == 0x0U);
2369 }
constexpr const auto mask
void dump() noexcept
auto is_allowed1() noexcept
void set(bool val) noexcept
auto is_allowed1() noexcept
void set(bool val) noexcept
constexpr const auto mask
Definition: cpuid_x64.h:85
constexpr const auto mask
auto is_allowed0() noexcept
auto is_allowed1() noexcept
auto is_allowed1() noexcept
auto allowed0()
constexpr const auto mask
auto is_allowed0() noexcept
constexpr const auto mask
constexpr const auto from
Definition: cpuid_x64.h:86
auto is_allowed0() noexcept
std::map< msrs::field_type, msrs::value_type > g_msrs
void set(bool val) noexcept
auto is_allowed0() noexcept
constexpr const auto mask
auto is_allowed0() noexcept
auto is_allowed1() noexcept
void set(T val) noexcept
constexpr const auto mask
auto get(A addr) noexcept
constexpr const auto mask
void set(A addr, T val) noexcept
auto is_allowed0() noexcept
auto get() noexcept
auto get() noexcept
constexpr const auto mask
auto get() noexcept
auto is_allowed1() noexcept
constexpr const auto addr
auto is_allowed0() noexcept
auto is_allowed0() noexcept
#define expect_false(a)
auto get() noexcept
void set(bool val) noexcept
auto get() noexcept
auto get() noexcept
auto allowed1()
auto is_allowed1() noexcept
auto get() noexcept
#define expect_true(a)
auto get() noexcept
auto get() noexcept
auto is_allowed1() noexcept