- s -

• secondary_processor_based_vm_execution_controls() : vmcs_intel_x64
• serial_port_intel_x64() : serial_port_intel_x64
• serial_ut() : serial_ut
• set() : register_state , register_state_intel_x64
• set_access_rights() : gdt_x64
• set_accessed() : page_table_entry_x64
• set_base() : gdt_x64
• set_baud_rate() : serial_port_intel_x64
• set_cr0() : vmcs_intel_x64_state
• set_cr3() : vmcs_intel_x64_state
• set_cr4() : vmcs_intel_x64_state
• set_cs() : vmcs_intel_x64_state
• set_cs_access_rights() : vmcs_intel_x64_state
• set_cs_base() : vmcs_intel_x64_state
• set_cs_limit() : vmcs_intel_x64_state
• set_data_bits() : serial_port_intel_x64
• set_dirty() : page_table_entry_x64
• set_dr7() : vmcs_intel_x64_state
• set_ds() : vmcs_intel_x64_state
• set_ds_access_rights() : vmcs_intel_x64_state
• set_ds_base() : vmcs_intel_x64_state
• set_ds_limit() : vmcs_intel_x64_state
• set_es() : vmcs_intel_x64_state
• set_es_access_rights() : vmcs_intel_x64_state
• set_es_base() : vmcs_intel_x64_state
• set_es_limit() : vmcs_intel_x64_state
• set_fs() : vmcs_intel_x64_state
• set_fs_access_rights() : vmcs_intel_x64_state
• set_fs_base() : vmcs_intel_x64_state
• set_fs_limit() : vmcs_intel_x64_state
• set_gdt_base() : vmcs_intel_x64_state
• set_gdt_limit() : vmcs_intel_x64_state
• set_global() : page_table_entry_x64
• set_gs() : vmcs_intel_x64_state
• set_gs_access_rights() : vmcs_intel_x64_state
• set_gs_base() : vmcs_intel_x64_state
• set_gs_limit() : vmcs_intel_x64_state
• set_ia32_debugctl_msr() : vmcs_intel_x64_state
• set_ia32_efer_msr() : vmcs_intel_x64_state
• set_ia32_fs_base_msr() : vmcs_intel_x64_state
• set_ia32_gs_base_msr() : vmcs_intel_x64_state
• set_ia32_pat_msr() : vmcs_intel_x64_state
• set_ia32_perf_global_ctrl_msr() : vmcs_intel_x64_state
• set_ia32_sysenter_cs_msr() : vmcs_intel_x64_state
• set_ia32_sysenter_eip_msr() : vmcs_intel_x64_state
• set_ia32_sysenter_esp_msr() : vmcs_intel_x64_state
• set_idt_base() : vmcs_intel_x64_state
• set_idt_limit() : vmcs_intel_x64_state
• set_ip() : register_state , register_state_intel_x64
• set_ldtr() : vmcs_intel_x64_state
• set_ldtr_access_rights() : vmcs_intel_x64_state
• set_ldtr_base() : vmcs_intel_x64_state
• set_ldtr_limit() : vmcs_intel_x64_state
• set_limit() : gdt_x64
• set_nx() : page_table_entry_x64
• set_parity_bits() : serial_port_intel_x64
• set_pat_4k() : page_table_entry_x64
• set_pat_index_4k() : page_table_entry_x64
• set_pat_index_large() : page_table_entry_x64
• set_pat_large() : page_table_entry_x64
• set_pcd() : page_table_entry_x64
• set_phys_addr() : page_table_entry_x64
• set_present() : page_table_entry_x64
• set_ps() : page_table_entry_x64
• set_pwt() : page_table_entry_x64
• set_rflags() : vmcs_intel_x64_state
• set_rw() : page_table_entry_x64
• set_ss() : vmcs_intel_x64_state
• set_ss_access_rights() : vmcs_intel_x64_state
• set_ss_base() : vmcs_intel_x64_state
• set_ss_limit() : vmcs_intel_x64_state
• set_state_save() : exit_handler_intel_x64
• set_stop_bits() : serial_port_intel_x64
• set_tr() : vmcs_intel_x64_state
• set_tr_access_rights() : vmcs_intel_x64_state
• set_tr_base() : vmcs_intel_x64_state
• set_tr_limit() : vmcs_intel_x64_state
• set_us() : page_table_entry_x64
• set_vmcs() : exit_handler_intel_x64
• setup_identity_map_1g() : root_page_table_x64
• setup_identity_map_2m() : root_page_table_x64
• setup_identity_map_4k() : root_page_table_x64
• size() : bfn::unique_map_ptr_x64< T > , mem_pool< total_size, block_shift > , memory_manager_x64
• size_map() : memory_manager_x64
• ss() : vmcs_intel_x64_host_vm_state , vmcs_intel_x64_state , vmcs_intel_x64_vmm_state
• ss_access_rights() : vmcs_intel_x64_host_vm_state , vmcs_intel_x64_state , vmcs_intel_x64_vmm_state
• ss_base() : vmcs_intel_x64_host_vm_state , vmcs_intel_x64_state , vmcs_intel_x64_vmm_state
• ss_limit() : vmcs_intel_x64_host_vm_state , vmcs_intel_x64_state , vmcs_intel_x64_vmm_state
• start() : vmxon_intel_x64
• stop() : vmxon_intel_x64
• stop_bits() : serial_port_intel_x64
• swap() : bfn::unique_map_ptr_x64< T >